A Framework for Memory Subsystem Exploration

Memory represents a major bottleneck in modern embedded systems in terms of cost, power and performance. Traditionally, memory organizations for programmable systems assume a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. However, such a processor-memory co-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, and perform exploration of the memory architecture to meet diverse requirements: low power, better performance, smaller die size etc. We present a set of experiments using our Memory-Aware Architectural Description Language to drive the exploration of the memory subsystem for the TI C6211 processor architecture, demonstrating a range of cost, performance, and energy attributes.